Scan registers (also known as scan flops or scan cells) are commonly used in integrated circuits (IC) to simplify the testing of manufactured IC chips. Scan registers are commonly used to enhance observability and/or controllability of a circuit during testing. Conventionally, a scan register is a register with both shift and parallel-load capability. The scan register may include a number of storage cells or latches to be used as observation points and/or control points.
An existing multiplexed-delay scan register is shown in FIG. 1. Referring to FIG. 1, the scan register 100 uses a Shift-Enable signal (SE) to configure the scan register 100 into a scan mode or a functional mode. The scan register 100 includes a multiplexer (MUX) 110, a master latch 120, a slave latch 130, and an inverter 140. In response to SE, the MUX 110 outputs either the scan-in data or the functional data as an input into the master latch 120. In response to the clock signal, the master latch 120 samples data from the MUX 110 on the negative edge of the clock signal and stores it therein on the positive edge of the clock signal during a clock cycle. That is, the master latch 120 samples data during low phase of the clock and stores data during the high phase of the clock. The master latch 120 then couples its output data into the slave latch 130. The inverter 140 inverts the clock signal into an inverted clock signal. The inverted clock signal is coupled to the slave latch 130 to control the sampling of data received from the master latch. In response to the inverted clock signal, the slave latch 130 samples data from the master latch 120 on the positive edge of the non-inverted clock signal and stores it therein on the negative edge of the non-inverted clock signal during a clock cycle. That is, the slave latch 130 samples data during high phase of the clock and stores data during the low phase of the clock. In this manner, the master latch can sample data while the slave latch stores data. Depending on whether the scan-in data or the functional data has been initially stored into the master latch 120 by way of the MUX 110, the slave latch 130 may drive out either the stored scan-in data or the stored functional data as Q/scan-out output.
A typical scan chain includes multiple scan registers, such as the scan register 100 in FIG. 1, coupled to each other in series. Test vectors can be shifted into the scan chain during the scan mode and the values stored in the scan registers in the scan chain are shifted out from the other end of the scan chain.
However, as the test vectors are shifted through the scan registers in the scan chain, the output of the scan registers change due to the 1's and 0's shifting through them. These changing values in the scan registers can cause excessive switching through the combinational logic network driven by the scan registers. This can draw excessive power and put extra strain on the power rails of the IC chip that may cause damage to the chip or invalidate test vectors due to voltage spikes affecting the state of registers. To reduce this impact, the test vectors are usually shifted in slowly.
One conventional solution to the above problem uses extra gating logic at the output of the scan register to reduce switching activity in the combinational logic network in scan mode during test. However, this solution adds extra delay in the scan register. Furthermore, enabling or disabling the scan mode in some existing scan registers can still cause excessive switching resulting in high peak power consumption. The additional logic may not be helpful in delay fault testing or system diagnosis using the scan registers.
Some existing techniques segmentize the scan registers into different scan chains and gate the clock signal for each of the scan chains differently to disable shifting the scan patterns through specific chains. However, this requires adding extra logic in a clock network that may complicate balancing the clock delay and minimizing clock skew across the IC chip. This technique also requires generation and reordering of the test vectors to allow some scan chains to disable their clock for portions of the test vectors.